Enabler: Enabling Energy Efficient Tunnel FET-CMOS Co-design by Compact Modeling and Simulation
This project is addressing the power dissipation as the greatest challenge for today's nanoelectronics, from a novel device and circuit hybrid design perspective. Tunnel FETs are steep slope switches that address critical power issues (especially the subthreshold power) in today.s and future nanoelectronics and are considered in research and industry as the candidate with the highest potential for low power circuits and systems. However, to achieve its full potential it is required to establish the modeling and simulation environment to understand the physics, optimize the device performance and be able to fully exploit the tunnel FET performance on the circuit and system level.
The ENABLER project is focusing on the development of a modeling and simulation environment necessary to enable to co-design of steep slope switches with advanced CMOS for novel energy efficient integrated circuits.
The goal of the NT Focused project is to establish the core physical modelling and derive basic compact DC models, calibrated and validated on nanowire tunnel naturopathy FETs, in order to enable the emergence of future hybrid Tunnel FET - CMOS IC design. Two state-of-the-art trends in the realization of tunnel FET architectures will be particularly followed: vitamin d (i) ultra-low power all-silicon (Si or SiGe source) device, integratable on advanced CMOS platforms, and, (ii) device based on III-V materials, also integratable into the future CMOS platforms that are expected to exploit novel super-mobility III-V material channels for n-MOSFETs. The ENABLER NTF project is foreseen to provide the modeling wheatgrass "glue" necessary for the success of the tunnel FET technology currently developed by IBM Zurich in Switzerland and various other technological efforts at EPFL.
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