Sub-Threshold Source-Coupled Logic (ST-SCL) Circuits for Ultra Low Power Applications (ULP-LOGIC)
NTF Research Program led by Prof. Yusuf Leblebici
ST-SCL/CMOS chip
Source: ©Y. Leblebici, EPFL
The demand for implementing ultra-low power digital systems in many modern applications such as mobile systems, sensor networks, and implanted biomedical systems, has made the design of logic circuits in sub-threshold regime a very important challenge.
This project explores the potentials of sub-threshold SCL (Source-Coupled Logic) circuits as an alternative solution for implementing ultra low power digital systems.
The utilization of ST-SCL circuits in shallow two-phase pipeline configuration also offers significant advantages in terms of power dissipation, by simply increasing the activity rate of the circuit. Combining this technique with variable supply current, we envision that the power dissipation (and the operating frequency) of critical circuit components can be scaled over a very wide range, for several orders of magnitude ? a feat that is completely impossible in conventional CMOS configuration.
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