Nano Tera Wiki: SummerSchoolProgrm

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""This five-day Summer School brings together instructors from renowned universities and research centres around the world with morning sessions dedicated to Nanoscale Electronics and afternoon sessions to Computer Aided Design. 
 
<a></a>Beyond CMOS Scaling - What's Next? H.-S. Philip Wong 
 
Scaling the silicon CMOS transistor has been the main driving force behind the progress of the microelectronics industry for over three decades. Today, the principal challenges for the semiconductor industry at the nanoscale are: (1) power and performance optimization, (2) device fabrication and control of variations at the nanoscale, and (3) integration of a diverse set of materials and devices on the same chip. 
 
Nanotechnology has been put forward as the key to meeting many of the challenges of the industry. New physical phenomena, materials, and chemical/biological synthesis techniques are being explored. While there have been significant accomplishments in scientific discovery at the nanoscale, the engineering work that is required to harness the science into manufacturable technologies is just beginning. 
 
Many new device technologies are being proposed for the continued progress of nanoelectronics. In this talk, a view of some of the more interesting options is given, including carbon nanotubes, semiconductor nanowires, steep subthreshold slope devices, and nanoelectromechanical relays. Recent progress is reviewed and the challenges ahead are outlined. The focus is on research work that needs to be done to bring these new technologies to fruition. 
 
<a></a>The Future of CMOS Scaling H.-S. Philip Wong 
 
While the device scaling rule proposed by Dennard was simple and elegant, the historical path of silicon CMOS device scaling has been anything but straight-forward. The early days of device scaling focused on geometric scaling, essentially following Dennard's proposed scaling scenario. The hot-carrier reliability problems brought on by the non-scaled power supply took years to overcome. By the 0.35µm era, the gate length was selectively and aggressively scaled down to gain performance. Dopant profile engineering had been the dominant technique to enable the next generation technology. By the 130 nm technology node, it became clear that new materials would soon be required and the industry went on the expedition to find the next gate dielectric to reduce gate leakage and new channel materials to improve carrier transport. Today, the strategy for 32 nm CMOS is high-k/metal-gate and more strain in the channel. 
 
With this historical perspective, I will explore what may be the key technological advances that may enable continued CMOS device scaling beyond the current paradigm. We believe that the historical rate of technology performance increase can be maintained by scaling the device footprint aggressively and by carefully engineering the device parasitic capacitance and parasitic resistance. In fact, we argue that device performance will increasingly be determined by parasitics and not the intrinsic device. Performance estimation and CAD tools will need to incorporate parasitics in first-order analyses. Details of the parasitic capacitance modeling for future CMOS devices will be presented. The new device scaling paradigm requires innovations in materials as well as fabrication technologies beyond the conventional lithography/etch/deposition suite of processes. 
 
Silicon quantum dots: the future of electronics and photonics? Shunri Oda 
 
Quantum dot structures, where electrons are confined three-dimensionally in the sub-10 nm scale, show characteristics quite different from conventional bulk structures. Recent progress in the fabrication technology of silicon nanostructures has made possible observations of novel electrical and optical properties of silicon quantum dots, such as single electron tunneling, ballistic transport, visible photoluminescence and electron emission. Electron transport and photonic properties of silicon nanocrystals prepared by plasma processes will be presented with particular emphasis on the fabrication of monodispersed silicon nanocrystals, high-density assembly of silicon quantum dots. I will also discuss applications of silicon quantum dots to nanodot memory for future Tera bit non-volatile memory devices, and silicon photonic devices for future ULSI interconnections. 
 
Novel Nano-<a class="missingpage" href="http://www.jocurile.us/cat-jocuri-cu-masini.htm">jocuri cu masini</a>-System Devices Shunri Oda 
 
A nanoelectromechanical device incorporating the nanocrystalline silicon (nc-Si) dots is proposed for use as a high-speed and nonvolatile memory. The nc-Si dots are embedded as charge storage in a mechanically bistable floating gate. Position of the floating gate can therefore be switched between two stable states by applying gate bias and its flip-flop motion can be sensed electrically by MOSFET underneath. Superior on-off characteristics are demonstrated by using an equivalent circuit model which takes account of the variable capacitance due to the mechanical displacement of the floating gate. Mechanical property analysis conducted by using the finite element method shows that introduction of nc-Si dot array into the movable floating gate results in reduction of switching power. High switching frequency over 1 GHz is achieved by decreasing the length of the floating gate to the submicron regime. I also present experimental demonstration of the mechanical bistability of the <a class="missingpage" href="http://www.nano-tera.ch/nanoterawiki/SiO2/edit" title="Create this page">SiO2</a> beams fabricated by using the conventional silicon etching processes. 
 
Classical versus Ballistic Transports Ken Uchida 
 
The physical gate length of modern, advanced MOSFETs is well less than 30 nm, and it is expected that the gate length will be less than 10 nm in 2016. In such short channel devices, charged carriers, which flow in MOS devices, will have less scattering events from source to drain. If no scattering occurs, this situation is called "ballistic transport". Whereas, in classical long channel devices, scattering events are frequent, and thus the carrier transport are strongly restricted by these events. Therefore, ballistic transport, namely no scattering, is an ideal situation for the carrier transport in advanced MOSFETs. In this talk, the relationship between classical and ballistic transports will be firstly shown. Then, the strategy to enhance current even in ballistic regime will be discussed. 
 
Performance Booster technologies for advanced MOSFETs: Stress Engineering and Surface Orientations other than (001) Ken Uchida 
 
The performance of MOSFETs have been improved by shrinking their dimensions. However, in recent years, the scaling of device sizes has less impact on the performance enhancement. Whereas, it has been realized that the enhancement of low-field mobility contributes to boost the MOSFET performance. Therefore, mobility booster technologies such as stress engineering and the utilization of surface orientations other than (001) have been attracting much attention. In this talk, stress engineering for higher-performance MOSFETs will be firstly introduced. Physical mechanisms for the electron/hole mobility enhancement by stress will be discussed, and then the optimum stress directions for higher-performance MOSFETs will be shown. Finally, the impact of surface orientation change on MOSFET characteristics will be reviewed. Particularity, electron/hole transport in (011) MOSFETs will be extensively discussed. 
 
Carbon Nanotube Interconnects for Next Generation ICs - Part I Kaustav Banerjee 
 
This lecture will highlight the issues and challenges related to nanoscale copper interconnects that is leading the search for new alternative materials. It will also provide a detailed introduction to carbon nanotubes (CNTs) and their attractive properties that make them a likely candidate to replace copper. It will also discuss the physical interpretation of resistance, capacitance and inductance in a CNT bundle and provide an overview of the state-of-the-art in the fabrication of single and multi-walled metallic CNT-bundle interconnects. 
 
Carbon Nanotube Interconnects for Next Generation ICs - Part II Kaustav Banerjee 
 
This lecture will discuss the state-of-the-art in CNT interconnect modeling and provide comparisons of their performance with respect to copper interconnects. It will present equivalent circuit models for both single and multi-walled CNT bundles and their delay analysis. High-frequency effects and their implications will be discussed in detail. Moreover, electro-thermal issues in CNT interconnects will be analyzed. Finally, some possible applications of CNT interconnects will be discussed. 
 
Silicon in vivo-Linking the world of microelectronics to that of living systems Kaustav Banerjee <a href="http://www.jocurile.us/joaca/jocuri-3d.html">jocuri 3D</a>
 
The worlds of microelectronics and biosystems have had very few, if any, common points. They indeed differ for materials (based on silicon rather than on carbon), information carriers (electron and holes rather than ions), length scales (0.1 μm rather than 10 μm), and time scales (10-8 s rather than 10-3 s). 
 
It is thus not strange that for many years microelectronics has ignored biology, at most considering biosystems as a source of contamination for rinsing water in device processing. Recently, however, the exponential growth of microelectronics has allowed, at least in principle, the construction of complex electronic systems with comparable size to that of the biosystem unit-the cell. The availability of such systems is expected to be able to produce a shift of paradigm in medicine. Order-of-magnitude feasibility calculations indicate indeed that nano-robots (artificial machines with overall size on the order of a few micrometres or less in all spatial directions and constituted by nanoscopic components with individual dimensions in the interval 1-102 nm) are not physically impossible [1]. Their availability "will finally give physicians the most potent tools imaginable to conquer human disease, ill-health, and aging" [2]. 
 
The talk is addressed to speculate on the possibilities and difficulties of this new world-silicon in vivo. 
 
[1] A. A. G. Requicha, "Nanorobots, NEMS, and Nanoassembly", Proc. IEEE 91, 1922-1933 (2003). 
[2] R. A. Freitas, Jr., "Current Status of Nanomedicine and Medical Nanorobotics", J. Comput. Theor. Nanosci. 2, 1-25 (2005). 
 
A roadmap to nanobiosensing Kaustav Banerjee 
 
The continuous endeavour toward size reduction and circuit complexity is expected to meet serious fundamental, technological or economic difficulties in the next 10 years. Within the current technological paradigm, based on the complementary metal-oxide-semiconductor (CMOS) technology, the progress seems possible, but requires huge economic investments. 
 
In their absence further progress seems still possible, but requires a shift of paradigm for both technology and circuit architecture. In particular, the crossbar architecture seems able to allow the production of circuits with bit density as high as 1011 cm-2, thus facing the tera scale integration (TSI). First objective of this talk is the detailed description of the major features of such a technology. 
 
Not only would the availability of circuits with TSI complexity open new conventional markets (e.g., simultaneous translation), but also would be exploitable for the sensing of biological systems at the sub-cellular level. Nanobiosensing, however, is not trivial and its achievement will certainly require an effort comparable with that involved in the development of microelectronics or of molecular biology. However, this endeavour is made easier by the fact that next-generation devices can be seen as nothing but scaled-down evolution of the ones of the previous generation. If not defined yet, a roadmap for nanobiosensing can therefore be hypothesized, thus rendering the research in this area of interest for industry. 
 
Pushing Nanoscale CMOS: Design-related Challenges Dennis Sylvester 
 
This talk will give an overview of the major challenges facing nanoscale CMOS in the sub-45nm regime from a design, and by extension CAD tool, perspective. Particular emphasis will be placed on power consumption, process variability, and reliability concerns. The inherent contradictions between low-power and robust design will be highlighted with views on how to resolve these contradictions in order to extend the lifespan of CMOS are presented. A central theme of the talk will be that successfully addressing nanoscale CMOS design concerns requires coordination across many levels of design, including devices, circuits, CAD, and architecture. 
 
Extending Nanoscale CMOS: Analyze, Sense, Correct, and Exploit Dennis Sylvester 
 
Building upon the earlier talk, this presentation will detail ongoing work that seeks to work around, or work with, the problems inherent in extremely scaled CMOS technologies. The topics range from the optimization of mechanically induced stress to improve performance or provide a better power/performance tradeoff point than is currently achieved, to efforts in creating reliable systems out of unreliable components that are based on massive in situ sensing of degradation. The talk will also touch on alternative paths to traditional statistical static timing analysis in light of process variability, demonstrating that intelligent sampling methods can lead to fast Monte Carlo-based timing analysis. 
 
Minimizing Leakage Power in CMOS: Technology Issues Massoud Pedram 
 
In many new designs, the leakage component of power consumption is comparable to the dynamic component. Many reports indicate that 50% or even higher percentage of the total power consumption is due to the leakage of transistors and this percentage will increase with technology scaling unless effective techniques are used to bring leakage under control. This talk will focus on circuit techniques and design methods to accomplish this goal. The first part of the presentation provides an overview of basic physics and technology, and scaling trends that have resulted in the significant increase in sub-threshold and gate leakage currents. The part provides an in-depth description of multiple, Vdd, multiple-Vt, and multiple Tox techniques for leakage minimization in light of process variations and substrate temperature changes. 
 
Minimizing Leakage Power in CMOS: Design Optimization Techniques Massoud Pedram 
 
The second part of this presentation describes a number of design optimization techniques for controlling leakage current, including, state assignment, technology mapping, and precomputation-based signal guarding. It will also present runtime mechanisms for leakage control including body bias control, transition to minimum leakage state, and power gating. 
 
Design for Nanotechnologies and 3D ICs Jason Cong 
 
In this talk, I shall first give an overview of the research in my group on design for nanotechnologies, as part of the ongoing project funded by the National Science Foundation jointly with Kang Wang (UCLA EE), Tim Cheng and Evelyn Hu (UCSB ECE). While most innovations in nanotechnology at this stage are primarily at the level of individual devices, we believe that it is at the systems level where the true potential of nanotechnology can be realized. Our research focuses on three areas - variability, reliability, and complexity of design for nanotechnologies and I shall highlight our progress in each of the three areas. 
 
In the second part of my talk, I shall present a thermal-aware 3D IC physical design system developed at UCLA in the past five years, including 3D floorplanning, 3D placement, and 3D routing with thermal via planning and insertion. I shall present our ongoing work on 3D microarchitecture exploration, based on the detailed physical prototyping using our 3D physical design tool and cycle-accurate architecture simulation. Preliminary study shows that for a simple out-of-order processor, the 3D design achieves 36% performance improvement over the 2D design with reasonable thermal control. 
 
Thermal-Aware 3D IC Physical Design and 3D Architecture Exploration Jason Cong 
 
In this talk, I shall give an in-depth discussion of our work on Thermal-Aware 3D IC Physical Design and 3D Architecture Exploration. In the first part of the talk, I shall present a thermal-aware 3D IC physical design system developed at UCLA in the past three years, including fast and efficient thermal modeling, 3D floorplanning, 3D placement, and 3D routing with thermal via planning and insertion. I shall discuss the key algorithms used in our 3D physical design tool and the results achieved by the tool in terms of interconnect reduction, density improvement, and thermal control and optimization. Our 3D physical design flow is being integrated into the IBM 3D design flow. 
 
In the second part of my talk, I shall present our ongoing work on 3D microarchitecture exploration, based on the detailed physical prototyping using our 3D physical design tool and cycle-accurate architecture simulation. We consider both tiling and folding of functional blocks in the 3D implementation, including 3D designs of complex functional blocks using word-line folding and port partitioning. We develop a cube packing engine which can simultaneously optimize physical and architectural design for effective utilization of 3D in terms of performance, area and temperature. Preliminary study shows that for a simple out-of-order processor, the 3D design over 30% performance improvement over the 2D design with reasonable thermal control. 
 
Beyond CMOS Scaling - What's Next? Subhashish Mitra 
 
One-dimensional nanodevices such as Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Si CMOS due to excellent device performance. A major gap exists between such single-device-level results and techniques required to harness the science into practical design technologies competitive with silicon-CMOS. An "ideal" CNFET technology can enable digital designs with 13X Energy-Delay-Product (EDP) advantage compared to 32nm Si-CMOS with same lithographic ground rules. However, fundamental challenges prevent us from creating efficient CNFET-based robust computing fabrics with anywhere close to above benefits. This talk will discuss major opportunities and challenges with CNFETs, and describe an interdisciplinary approach to overcome the challenges by combining imperfection-immune design techniques with CNFET modeling and processing. We will also <a href="http://www.jocurile.us/cat-jocuri-barbie.htm">jocuri barbie</a> present experimental demonstration of essential components and their integration for large-scale CNFET technology. 
 
The Future of CMOS Scaling Subhashish Mitra 
 
Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to silicon-CMOS for two major reasons: 
1. CNFETs can provide significant energy and performance benefits over traditional CMOS, and 2. CNFET processing is compatible with existing CMOS processing flows. Two fundamental barriers that prevent us from creating digital designs at VLSI scale using CNFETs are: 1. Misaligned and mis-positioned Carbon Nanotubes (CNTs), and 2. Metallic CNTs. Misaligned and mis-positioned CNTs can result in incorrect logic implementations. Metallic CNTs create resistive source-drain shorts in CNFETs, causing excessive leakage, severely degraded noise margins, and delay variations. In this paper, we introduce an imperfection-immune design paradigm to overcome these barriers. We present a design technique, together with experimental demonstration, for creating CNFET logic circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mis-positioned CNTs. We also describe techniques for co-optimizing CNT processing and circuit design in order to derive practical design guidelines for metallic-CNT-tolerant digital circuits. These techniques are very inexpensive compared to traditional defect- and fault-tolerance techniques, do not impose major changes in VLSI design flows, and are compatible with VLSI processing because they do not require special customization on a chip-by-chip basis. 
 
A roadmap for 3D technologies and their design opportunities Paul Marchal 
 
3D integration offers numerous opportunities for design, and is probably the best hope for carrying ICs along (and even beyond) the path of Moore's Law in the 21st century. However, many questions still need to be answered to take advantage of 3D. First, what will become the mainstream 3D technology? Today, many technology options are proposed, but each having different cost, design and implications. Secondly, how to make 3D designs reliable? Many unknowns still exist related to thermal load, reliability and signal integrity challenges. Finally, what about design solutions/methods and architectural modifications for 3D integration? In this talk, an attempt will be made to roadmap 3D technologies and their design implications. 
 
Path Finding - a design/technology co-exploration Paul Marchal 
 
To identify the 3D technology options that best fit the target system, it is mandatory to co-explore both technology and design options. The contribution of this talk is to introduce a path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3D case study. Initial results will be presented that demonstrate the benefits of the proposed path finding methodology to steer the technology development and fine-tune design strategies. 

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Nano Tera Wiki : SummerSchoolProgrm

Formatting code for SummerSchoolProgrm