Formatting code for ULPSystems
====ULP-Systems: Sub-Threshold Source-Coupled Logic (ST-SCL) Systems for Ubiquitous System Applications====
{{image url="http://www.nano-tera.ch/images/uploads/311/311.png" title="text" alt="text"}}
The demand for implementing ultra-low power digital systems in many modern applications such as mobile systems, sensor networks, and implanted biomedical systems, has made the design of logic circuits in sub-threshold regime a very important challenge. In sub-threshold MOS devices, current density is very low and the ratio of the transconductance to bias current of the device (gm/ID) is maximum. Meanwhile, the exponential relationship between drain current and gate voltage can make them very suitable for implementing widely adjustable circuits. CMOS logic circuits utilizing subthreshold transistors can operate with very low power consumption. In this
{{image url="http://www.nano-tera.ch/images/uploads/311/311.png" title="text" alt="text"}}
The demand for implementing ultra-low power digital systems in many modern applications such as mobile systems, sensor networks, and implanted biomedical systems, has made the design of logic circuits in sub-threshold regime a very important challenge. In sub-threshold MOS devices, current density is very low and the ratio of the transconductance to bias current of the device (gm/ID) is maximum. Meanwhile, the exponential relationship between drain current and gate voltage can make them very suitable for implementing widely adjustable circuits. CMOS logic circuits utilizing subthreshold transistors can operate with very low power consumption. In this