Todays micro/nano-electronics is characterized by migration of research from pure down-scaling to new functionality and combined technology-system innovation. This is mainly required in order to manage power dissipation, variability and complexity issues that are associated with tera-systems that exploit nano-technology. While this new functionality and technology-system innovation will exploit the properties of future nano-scaled technologies, the aggressive scaling will also play a fundamental, but not an exclusive role. New research drivers, such as ultra-low power technologies, bio-inspired circuit and system design and ambient intelligence applications are expected to play an increasingly important role in the next years.

The generally accepted view of micro and nano-electronics identifies three main research domains: (i) More Moore, (ii) Beyond CMOS and (iii) More than Moore.

The More Moore domain is essentially dealing with technologies related to the nanometer CMOS; prevailing business directions together with continuing scalability have determined the evolution of silicon CMOS as the technology with the highest added value. In Nano-Tera.CH, CMOS technology will be considered as a key platform to supply the massive computing power and communication capability needed for the realization of Ambient Intelligence applications at an affordable cost and a power efficiency exceeding todays leading-edge examples.

The Beyond CMOS domain deals with disruptive technology and device principles (from charge to non-charge based devices, from semiconductor to molecular technology), compared to CMOS, to exploit atomic-scale technology and novel functionality. Novel switches, architectures for universal memory and new interconnect approaches are some of the identified challenges. In addition to technologies such as nanowires and nanotubes, particular attention will be devoted to the development of disruptive technologies such as molecular electronics, over a longer time horizon. In this perspective, partial (hybridization) or total replacement solutions for silicon CMOS are foreseen.

The More than Moore field is of strategic relevance for Nano-Tera.CH; it deals with true engineering of complex systems that combine, by heterogeneous integration techniques, various technologies. The More than Moore technology platform also gives particular attention to MEMS/NEMS and sensor technologies that are combined to silicon or non-silicon computing, information storage and encryption and wireless / RF communication technologies.

Major micro/nano-electronic research priorities for Nano-Tera.CH are organized and discussed in three sections:

  1. Technology (top down and bottom up)
  2. Devices and Circuits
  3. Systems and Integration.


Within the last decade, the nanotechnology and nanodevice evolutions have been dominated by the aggressive scaling in the sub-100nm zone and the related cost-effectiveness of silicon technology. Today top-down nanolithographic based approaches are challenged by bottom-up nanotechnology; Nano-Tera.CH considers that a smart combination and developments of the two approaches will be needed in the future and the choices will be dictated by complex system performance and functionality. Atomic-scale technologies with nano-to-micro interface technologies and the possible extension of the Moores law in the 3rd dimension for building tera-systems are ultimate goals of the fabrication research and development. Below, some of the most important topics in nanotechnology are discussed.

Top-Down (mostly silicon based): Presently, silicon top-down technology (Nanometer CMOS) is the single recognized solution for reliable circuits and systems. In order to meet the challenges of near-10nm gate length , the Nanometer CMOS will have to integrate the so-called technology boosters, such as high-k metal gate stacks and transport enhancement techniques (strained devices and bandgap engineering). Top-down etched silicon nanowires or the integration of III-V nanowires on silicon CMOS will then become alternative platforms on which 3D nano-processing (such as in the case of Gate-All-Around nanowire transistors), process control, abrupt junction (smaller than 2nm) and metal contacting will have to deal with tolerable variability and high density. Other top down techniques, such as nano-imprint and nano-stenciling will have to be considered as alternative to e-beam or other advanced lithography.

Bottom-Up: Bottom up nanotechnology is a unique opportunity for nanoelectronics to develop and exploit self-assembly approaches, which could offer unrivaled density of functionality beyond lithographic limits. In the this context, the exploration of both organic and inorganic materials, the nanowire and nanotube growth and self-assembling techniques of these one dimensional structures, the possibility offered by semiconducting or metallized DNA technology and the controlled fabrication and exploitation of 0-dimensional structures (nanodot technology) are clear identified priority domains. In general, molecular electronic technologies that answer the computation, memory and interconnectivity challenges to build and serve for true tera-scale systems, will be considered as future alternative of silicon CMOS, under the nanoelectronics umbrella.

On top of those, other realistic emerging fabrication techniques and related materials for large area electronics, where the global dimensionality of the system is completely different, such as direct printing techniques and ink-jetting (using semiconducting and conducting inks based on nanoparticles), with applications in flexible electronics, or enabling advanced concepts as invisible or paint-able electronics, will be considered.

Devices and Circuits

Novel devices and circuit architectures, truly exploiting the new emerging technology are key aspects of Nano-Tera.CH research because of their impact in all application domains and of the possibility to create unique know-how around the new concepts. While in the digital domain the world-wide research is dominated by the quests for the new quasi-ideal switch and the so-called universal memory (a memory concept that is non-volatile and able to integrate all the microprocessor memory hierarchy, including the slow external drive, on a single dense and high-speed memory platform), Nano-Tera.CH will also consider, on top of those, the device quest for new functionality and ultra-low power.

Ultra low-power devices and circuits exploiting both solid-state but also hybrid principles (where electronics is combined with micromechanics, optics, spin devices, etc) will enable standby power levels that are compatible to the practical requirements of the wireless sensor nodes (sub-100microW/node) and the true possibility of considering energy scavengers at the scales of power. New switch devices such as tunnel FET, NEM-FET, IMOS or, at much longer term, some more exotic device architectures exploiting discrete charge, such as Single Electronics or QCA-like, could play a significant role in this context. Finally, it is worth mentioning that, in general, individual molecular devices appear promising for future high-dense ultra-low power electronics; particular attention will be paid to the demonstration of novel circuit and system architectures exploiting the unique molecular device features (for instance, the possible use of molecular switches in cross-bar memory architecture, enabling an increase of memory density by 102 compared to any other conventional approach).

High-speed and telecom devices and circuits operating at frequencies in excess of hundreds of GHz, and approaching the THz regime, will be essential for enabling communication interfaces and More-than-Moore system solutions. Co-design of analog ICs with RF MEMS devices (for tunable/programmable RF front-ends and also, including antenna technology) will be there essentially for achieving both high frequency (HF) and low power operation. These new devices are expected to open an era of electro-mechanical signal processing and, especially, HF system reconfigurability.

A particularly important category is the bio-inspired devices and circuits; in this direction, priorities will be given to the increase of the local inter-connectivity of individual devices, such as in the neuron-inspired devices case and the processing of the information using principles other than the binary logic (analog or weighted multiple input approaches; neural-inspired circuits, in general). In the case of these architectures, the targeted performance factors will be not primarily related to high speed but rather parallel processing of information at extremely low power and 3D device and circuits architectures.

Universal memory device architectures and related addressing circuits is so far identified as a strategic research direction in micro/nanoelectronics; this is motivated by the fact that all the tera-system applications are requiring today huge amount of memory, as dense as possible and very high-speed. Moreover, today there is no clear winner in the quest for the universal memory; PCM/OUM (phase change/ovonic), FLASH, MRAM (magnetic RAM), FeRAM (Ferroelectric RAM), polymer memories, Millipede, etc., are all competing in an increasing market of non-volatile memories.

Disposable electronics and applications in monitoring (security) and the medical field are expected to be supported by the category of flexible and large-area electronics. Ultra-thin film organic and non-organic materials (integrable on flexible substrate) with high carrier mobility, low voltage operation, the control of device lifetime and of the drift of characteristics of these devices, their processing with ultra low temperature budget (less than 200C) and the co-integration of digital, analog, sensing, memory and communications functions on flexible substrates, all are challenges to be addressed in the future.

Systems and Integration

Innovative breakthrough ideas that enable true tera-scale system integration will play a central role in Nano-Tera.CH, opening up the possibility of achieving system complexities that are two-to-three orders of magnitude higher than todays state-of-the-art. This capability is absolutely key for the successful demonstration of the fabrication technologies and novel device/circuit concepts that are explored under the umbrella of the research initiative. Equally important, the systems integration aspect will be used as a touchstone for evaluating and for qualifying various nano-scale device technologies, in the sense of determining the system-ability of such candidate technologies.

3-dimensional (3D) and vertical integration of nanoelectronic devices, memory elements, and interconnect layers is considered as a very promising technique to increase the overall integration density as well as the performance of complex systems, mainly due to the significant shortening of connection paths between layers (strata). However, a number of very challenging issues will need to be resolved in order to allow widespread adoption of 3D integration for large-volume production: realization of high-density thru-wafer vias, multi-level wafer bonding techniques, addressing the thermal management issues for intermediate layers, development of effective 3D layer assignment, placement and 3D routing algorithms to mention a few. True 3D integration is expected to open the possibilities for very-small-form-factor multi-processing and memory units which can be used in wearable / ubiquitous systems as well as implanted devices. This 3D integration aspect will also become one of the central technology drivers of the Nano-Tera.CH initiative that will be utilized to merge many technology layers.

Heterogeneous integration platforms: In parallel to the development of nanometer CMOS as well as beyond-CMOS device technologies for switching, memory and analog functions, there is an increasing need to integrate various (heterogeneous) technologies without sacrificing the overall system performance and without further increasing the packaging costs. This may be accomplished by the judicious use of wafer bonding techniques, multi-chip packages, optical and electro-magnetic coupling between various components for high data transfer rates and improvement of SiP technologies. This becomes especially valuable when considering integrated MEMS/NEMS devices that must interface with the processing electronics in very close proximity, and in RF/wireless applications.

Reliability and fault tolerance of future complex systems built with nanoscale electronic devices cannot be guaranteed using conventional measures, due to fundamental physical limitations such as process variability, excessive leakage, process costs as well as very high power densities. This observation calls for radical action on several fronts in order to ensure the continuity of the nanoelectronic systems integration paradigm. In particular, under Nano-Tera.CH we will develop circuit-level measures to mitigate the limitations of process variations, leakage and reduced device reliability; and finally, explore system-level design approaches that are better adapted to the constraints imposed by the materials, technology, and device physics.

Thermal control / power-energy management: Power/energy dissipation of complex integrated systems continues to be the primary show-stopper at high speed, and also for wearable-implantable systems. The power/energy optimization of multi-core integrated systems will require continuous monitoring of the actual workload conditions and judicious choices for the operating voltage as well as the frequency of each computing element. Ground-breaking technological innovations (such as on-chip Peltier elements, or liquid cooling through micro-channels) as well as systematic implementation of aggressive power management techniques (such as on-line temperature monitoring/control and schedule optimization) will be needed to address these problems within the frame of the Nano-Tera.CH initiative. In particular, it is expected that future digital and mixed-signal circuits and systems will make extensive use of subthreshold (weak-inversion) mode operation, exploiting ultra-low-current techniques and massive parallelism (system-level multiplexing) to achieve high performance at a low power budget.

Wireless / RF systems: With ubiquitous and wearable systems as a main target area, it is envisioned that the low-power high data-rate wireless communication techniques and systems will play a decisive role for the realization of many demonstrator applications, within the frame of Nano-Tera.CH. Key issues that will be addressed include ultra-wide-band (UWB), extreme low-power RF front-end design for wearable applications, utilization of hybrid integration technologies such as RF-MEMS/NEMS components, wireless sensors, as well as RF-based energy transfer / energy scavenging.

Bio-medical interfaces / implantable systems: Development of efficient bio-medical interfaces involves the exploration of bio-compatible materials, possible utilization of nanoscale components such as CNTs, as well as ultra-low-power and ultra-low-noise electronics to sense and convert the biological signals without disturbing or interfering with the living tissue. The developed technologies in this field are expected to be instrumental for a wide range of implanted and portable analytic devices, such as DNA and protein sensors, diagnostic Lab-on-a-Chip (LoC) devices and neuronal/electronic interfaces for therapeutic applications.

Optical interconnects / optical clock distribution: In high-density, high-performance digital systems, short distance (chip-to-chip and board-to-board) optical interconnects are driven by the need for larger bandwidth and better cross-talk immunity. For on-chip optical interconnects, more fundamental challenges will have to be addressed such as the technological feasibility of silicon-based emitters and receivers, suitability of waveguide materials, and power dissipation limitations. Key challenges for optical clock distribution include the layout of a regular distribution network, placement of clock receivers/repeaters, and the design of high-efficiency silicon photodetectors.

Computer-Aided design: Models, algorithms, tools and methodologies are needed to support experimental and production-level design with nano-technologies.  Nano-Tera.CH will foster the developments of technologies for design (design technologies) that provide appropriate abstraction of the technology to support simulation (at various levels) of devices and circuits, as well as the synthesis of their physical design. At the same time, design methods and tools to support logic design on nano-technologies, wit h specific attention to parallelism, redundancy and reliability issues.

It is worth mentioning that Nano-Tera.CH will pay particular attention to the benchmarking of new technology and devices according to given system level functionality and specifications; a so-called system-able micro/nano-electronics approach will be the key for success. Some of the criteria for filtering out the true system-able nanotechnologies include: Ability to co-host/co-integrate three basic system functionalities: computation, storage and communication (interconnects); acceptable power density and/or energy consumption; device variability and cost-effective solutions; possibility to build analog or mixed signal systems from the new devices; reliability and yield adequate for envisioned applications; and the added value with respect to silicon CMOS.

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