Summer School on Microscale Cooling of 3-D integrated systems
June 5-10, 2011
Training of the future generation of 3D Integrated Circuit and Cooling engineers and researchers requires a dedicated effort to bring together the PhD students of the various important disciplines involved in this technology’s development (Electrical engineering, electronics engineering, mechanical engineering, micro-manufacturing). With the advent of 3D-IC architectures with interlayer cooling (microchannel cooling passages inside the architecture on each layer), top PhD’s and researchers must have a common base knowledge of microscale heat transfer, interlayer cooling, 3D modeling, and thermal management together with similar knowledge of the important 3D manufacturing technologies, such as that of TSVs, etching of microchannels in silicon wafers, etc. The present Summer School aims at providing this education. Traditionally, 2D-ICs have been first designed by micro-electronic engineers and then handed to thermal packaging engineers (usually mechanical engineers) for their add-on cooling system. While this was okay for one-layer cooling, this sequential approach does not work for 3D architectures with cooling channels inside the 3D stack where the microchannels have to be placed correctly to not interfere with the TSVs and to cool the local hotspots of a multi-layered stack of eventually 20 or more layers. Furthermore, in 3D architectures, thermal management also needs to be integrated into the development process at step one of the process besides of course the micro-fabrication techniques of TSV’s, etc.