EPFL/STI/IEL/LSM
Expert in chip design, intelligent detector, VLSI design, high-level specification and synthesis, sensors development
Yusuf Leblebici
EPFL
FEDAMaT
2011 Nano-Tera Workshop on Future Electronic Design Automation Methodologies and Tools (FEDAMaT)

Computer and Communications Engineering
Expert in high-performance low-power hardware architecture
Georgios Stamoulis
Computer and Communications Engineering

Project Description

This project provides a comprehensive sequence of immersion courses into the new obstacles a designer encounters in the sub-45nm region and the new CAD tools and methodologies required to extract the most value out of the ever shrinking integrated circuit fabrication processes. The target audience will be the EPFL/ETHZ circuit design community with a three tier approach: initially a graduate/Ph.D. level course will be used to introduce the emerging design constraints and highlight the drawbacks of current CAD tools and design methodologies. This will be followed by a dense five-day summer course where industry and research leaders will introduce novel approaches for tackling the aforementioned drawbacks and provide insight into the finer details of future design and fabrication processes. The learnings of the summer course will be then applied towards optimizing designs with the currently available approaches and then by the new ones, quantifying the gains in performance, power, as well as circuit reliability and fabrication yield, in another graduate/Ph.D. level course for a selected set of students. 

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