ULP-Systems: Sub-Threshold Source-Coupled Logic (ST-SCL) Systems for Ubiquitous System Applications

The demand for implementing ultra-low power digital systems in many modern applications such as mobile systems, sensor networks, and implanted biomedical systems, has made the design of logic circuits in sub-threshold regime a very important challenge.

In sub-threshold MOS devices, current density is very low and the ratio of the transconductance to bias current of the device (gm/ID) is maximum. Meanwhile, the exponential relationship between drain current and gate voltage can make them very suitable for implementing widely adjustable circuits.

CMOS logic circuits utilizing subthreshold transistors can operate with very low power consumption. In this type of circuits, the power dissipation is mainly due to the dynamic (switching) power consumption and is quadratically dependent to the supply voltage. Hence, reducing the supply voltage will result in reduction of power dissipation as well as the output logic swing. Supply voltage reduction, on the other hand, increases the delay in each gate which means the power dissipation, logic swing, and speed of operation are tightly related to each other. Meanwhile, the exponential relationship between power dissipation and supply voltage in sub-threshold regime makes the accurate control of power consumption difficult. To implement very low power digital systems, it is necessary to minimize the energy dissipation at the system level in addition to the gate level to achieve the desired performance.

Source-coupled logic (SCL) circuits are widely used in mixed-mode integrated circuits where the supply and substrate noise injection are crucial. Reduced output voltage swing in SCL circuits compared to the CMOS logic gates has made this topology very suitable for high frequency applications. This project explores the potentials of sub-threshold SCL circuits as an alternative solution for implementing ultra low power digital systems. In this approach, the power consumption and maximum speed of operation can be adjusted linearly through the tail bias current of each gate over a very wide range, thus, efficiently decoupling the decision of output voltage swing from power dissipation and delay.

The earlier research results obtained at LSM under Nano-Tera funding indicate that the operating current dissipation of logic cells can be reduced to levels as low as 1-10 pA, and that the power-delay product of a typical ST-SCL gate can be well below 1 fJ. This suggests that the proposed circuit topology has a very significant potential for ultra low-power applications, especially in circuits where the operating (clock) speed is not very high, and where the energy supply is limited. The ability to de-couple the power dissipation from the output voltage swing also provides an additional degree of freedom when considering frequency-scaling techniques to match the operation speed of the circuit to available energy. Since the dissipation of the circuit can be effectively controlled by adjusting the tail bias current alone, a simplecontrol feedback can provide the possibility to adjust the supply current (and consequently, the operating speed) of the circuit without affecting the operating voltage range. This opens up completely new possibilities for dynamic power scaling under strict energy constraints.

The utilization of ST-SCL circuits in shallow two-phase pipeline configuration, demonstrated during the past year, also offers significant advantages in terms of power dissipation, by simply increasing the activity rate of the circuit. Combining this technique with variable supply current, we envision that the power dissipation (and the operating frequency) of critical circuit components can be scaled over a very wide range, for several orders of magnitude, a feat that is completely impossible in conventional CMOS configuration.

Preliminary results have shown that the ST-SCL circuit topology has a very wide application range covering logic, memory, mixed-signal functions as well as PLLs and continuous-time filters. Thus, the proposed circuit design approach has the promise of developing into a complete platform for ultra-low power ubiquitous system applications.

posters from 2011

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