PlaCiTUS: Platform Circuit Technology Underlying Heterogeneous Nano and Tera Systems
Project Leader: Qiuting Huang of ETHZ/Integrated Systems Laboratory (IIS) T: +41 44 632 5240
Catherine Dehollain of EPFL/STI/GR-SCI-STI/SCI-STI-CD, expert in Wireless electronics, RFID-circuit design, Low-power physiological sensing
Christian Enz of CSEM, expert in wireless sensor networks, very low-power analog IC design and semiconductor device modeling
The revolution in information and communication technology that is taking information flow into the era of tera-bits and the biomedical advances down to molecular scale would not have taken place without the accompanying downscaling of CMOS technology to the nano scale device size and tera system complexity. This aggressive downscaling has allowed the number of transistors per chip to be increased, thus extending their functionality and pushing up speed performance. However, this is obtained at the cost of severe degradation in certain quality metrics, such as increase of parameter variability, strong degradation of device matching, and increase in leakage currents including gate leakage, stronger short-channel effects (weak-inversion slope reduction, drain-induced barrier lowering, etc), ever lower supply voltage, novel degradation mechanisms and increasing reliability constraints. The profound changes in the device structure that are required to mitigate or eventually circumvent all these degradations will obviously have a significant impact on the way circuits, and particularly analog and RF circuits, have to be designed.
It is therefore crucial to fully understand the operation and limitations of these devices in order to design robust digital, analog and RF circuits. In the next decade, the challenges to the semiconductor industry and the applications it supports will lie not so much in realizing smaller and faster transistors as in how to make the best out of the billions of transistors per chip we already have. Understanding how to handle complexity in mixed signal embedded systems is therefore crucial for the next generation of applications that deal with health, microsystems and communications. How to partition system functionality into digital, analog and RF or sensor realizations on a system on chip optimally is one of the key topics that will impact the era of nano CMOS technologies.
This project investigates the challenges in mixed signal platforms, such as those embedded in biomedical electronics, micro-systems, sensor networks and wireless communications, from both device and systems perspective. Demonstrators will be developed that cover generic sensor interface/data acquisition, passive telemetry, wireless body area network, wireless sensor networking and wireless wide area networks. The achievements will benefit other Nano-Tera projects focusing on the sensor/actuator side of microsystems, as well as wireless communications SoCs that will challenge the state-of-the-art in integration level, versatility and sophistication of nano CMOS systems.
A 2.4-GHz BAW-Based Transceiver for Wireless Body Area Networks M. Contaldo, B. Banerjee, D. Ruffieux, J. Chabloz, E. L. Roux, and C. C. Enz IEEE Trans. on Biomedical Circuits and Systems, (0, 2010)
The revolution in information and communication technology that is taking information flow into the era of tera-bits and the biomedical advances down to molecular scale would not have taken place without the accompanying downscaling of CMOS technology to the nano scale device size and tera system complexity. This aggressive downscaling has allowed the number of transistors per chip to be increased, thus extending their functionality and pushing up speed performance. However, this is obtained at the cost of severe degradation in certain quality metrics, such as increase of parameter variability, strong degradation of device matching, and increase in leakage currents including gate leakage, stronger short-channel effects (weak-inversion slope reduction, drain-induced barrier lowering, etc), ever lower supply voltage, novel degradation mechanisms and increasing reliability constraints. The profound changes in the device structure that are required to mitigate or eventually circumvent all these degradations will obviously have a significant impact on the way circuits, and particularly analog and RF circuits, have to be designed.
