Indicators show that the speed of transistor density and microprocessor performance improvements that drove the IT industry for the last 50 years are now limited by connectability issues between multiple cores and air-cooling rates. With its CMOS scaling engine slowing, the industry is striving to find new packaging altenatives to maintain the overall pace according to Moore’s law. While 2D scaling has been used in high performance processors for several decades, the third dimension has not yet been tackled. Recent progress in the fabrication of through silicon vias has opened new avenues for high density area array interconnects between stacked processor and memory chips. Such three-dimensional integrated circuits are attractive solutions for overcoming the present barriers encountered in interconnect scaling, thus offering an opportunity to continue the CMOS performance trends over the next few decades.
Water Nanoconfinement Induced Thermal Enhancement at Hydrophilic Quartz Interfaces M. Hu, J. V. Goicochea, B. Michel, D. Poulikakos, Nano Letters (2010)
Validation of the Porous-Medium Approach to Model Interlayer-Cooled 3D-Chip Stacks T. Brunschwiler, S. Paredes, U. Drechsler, B. Michel, W. Cesar, G. Töral, Y. Temiz, Y. Leblebici, IEEE International Conference on 3D System Integration (3DIC 2009), (2009)
Two-phase flow boiling of R134a in a multi-microchannel heat sink for microprocessor cooling Y. Madhour, J. Olivier, E.C. Patry, S. Paredes, B. Michel, J.R. Thome, THERMINIC Conference (2010)
Two-phase flow boiling of R134a in a multi-microchannel heat sink for microprocessor cooling Y. Madhour, J. Olivier, E.C. Patry, S. Paredes, B. Michel, and J.R. Thome, THERMINIC Conference Proceedings (2011)