CMOSAIC: 3D Stacked Architectures with Interlayer Cooling
Project Leader: John Thome of EPFL/STI/IGM/LTCM +41 21 693 5981
David Atienza of EPFL/STI/IEL/ESL
, expert in thermal modeling of multiprocessor architectures and thermal management, hardware/software co-design methods
Yusuf Leblebici of EPFL/STI/IEL/LSM, expert in Chip Design. Intelligent Detector. VLSI Design. High level specification and Synthesis-sensors development
Bruno Michel of IBM Zürich [Industrial Partner], expert in thermal packaging of high performance computers
Dimos Poulikakos of ETHZ/D-MAVT/IET/LTNT, expert in micro-scale liquid phase cooling, nanofluid heat transfer and heat transfer modeling
Jan Wendelin Stark of ETHZ/DCHAB/ICB/FML, expert in catalyst nanoparticles, nanomaterials and conception and characterization of nanofluids
Indicators show that the speed of transistor density and microprocessor performance improvements that drove the IT industry for the last 50 years are now limited by connectability issues between multiple cores and air-cooling rates. With its CMOS scaling engine slowing, the industry is striving to find new packaging altenatives to maintain the overall pace according to Moore’s law. While 2D scaling has been used in high performance processors for several decades, the third dimension has not yet been tackled. Recent progress in the fabrication of through silicon vias has opened new avenues for high density area array interconnects between stacked processor and memory chips. Such three-dimensional integrated circuits are attractive solutions for overcoming the present barriers encountered in interconnect scaling, thus offering an opportunity to continue the CMOS performance trends over the next few decades.
The CMOSAIC project is a genuine opportunity to contribute to the realization of arguably the most complicated system that mankind has ever assembled: a 3D stack of computer chips with a functionality per unit volume that nearly parallels the functional density of a human brain. The aggressive goal is to provide the necessarily 3D integrated cooling system that is the key to compressing almost 1012 nanometer sized functional units into a 1 cm3 volume with a 10 to 100 fold higher connectivity than otherwise possible. Even the most advanced air-cooling methods are inadequate for such high performance systems where the main challenge is to remove the heat produced by multiple stacked dies with each layer dissipating 100-150 W/cm2. Therefore, state-of-the-art microscale single-phase liquid and two-phase cooling systems are being developed, using specificaly designed microchannel arrangements with channel sizes as small as 50 microns. The employed coolants range from liquid water and two-phase environmentally friendly refrigerants to novel nano-coated, nonwetting surfaces. To this aim, CMOSAIC has brought together a multi-disciplinary team of internationally recognized experts who are jointly conducting research to explore the underlying physics of the proposed cooling mechanisms through experiments and theoretical modelling. The team will also develop all the necessary modelling and design tools needed to simulate 3D integrated circuits stacks during their operation in order to mitigate hot spots, and test various prototype stacks with the goal of identifying and bringing into reality novel methods for heat removal in these high performance systems.
Attaining Single-Chip, High-Performance Computing Through 3D Systems with Active Cooling A. K. Coskun, D. Atienza, M. Sabry, J. Meng, IEEE Micro Magazine, ISSN: 0272-1732, IEEE Press, (7, 2011)
Energy-Efficient Multi-Objective Thermal Control for Liquid-Cooled 3D Stacked Architectures M. Sabry, A. K. Coskun, D. Atienza, T. Simunic, T. Brunschwiler IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), IEEE Press, (11, 2011)
Experimental investigation into vortex structure and pressure drop across microcavities in 3D integrated electronics A. Renfer, M. K. Tiwari, T. Brunschwiler, B. Michel, D. Poulikakos, Experiments in Fluids, (0, 2011)
Surface Functionalization Mechanisms of Enhancing Heat Transfer at Solid-Liquid Interfaces J. V. Goicochea, M. Hu, B. Michel, D, Poulikakos Journal of Heat Transfer, (0, 2011)
3D integrated water cooling of a composite multilayer stack of chips F. Alfieri, M.K. Tiwari, I. Zinovik, D. Poulikakos, T. Brunschwiler and B. Michel, Journal of Heat Transfer. (0, 2010)
A novel time strip flow visualisation technique for investigation of intermittent dewetting and dryout in elongated bubble flow in a microchannel evaporator N. Borhani, B. Agostini, J.R. Thome, International Journal of Heat and Mass Transfer, (0, 2010)
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling P.G. Del Valle, D. Atienza, Elsevier Microelectronics Journal, ISSN: 0026-2692, (0, 2010)
Flow boiling of R134a in a multi?microchannel heat sink with hotspot heaters for energy?efficient microelectronic CPU cooling applications Y. Madhour, J. Olivier, E. Costa?Patry, S. Paredes, B. Michel, and J.R. Thome, IEEE Transactions on Components, Packaging and Manufacturing Technologies, (0, 2010)
Thermal-Aware Compilation for Register Window-Based Embedded Processors M. Sabry, J. L. Ayala, D. Atienza Embedded Systems Letters, IEEE Press, ISSN: 1943-0663, Vol.2, Issue/Nr. 4, pp. 103-106, DOI: 10.1109/LES.2010.2081343, (12, 2010)
Water Nanoconfinement Induced Thermal Enhancement at Hydrophilic Quartz Interfaces M. Hu, J. V. Goicochea, B. Michel, D. Poulikakos, Nano Letters (0, 2010)
Thermal Rectification at Water Functionalized Silica Interfaces M. Hu, J. V. Goicochea, B. Michel, D. Poulikakos, Applied Physics Letters (0, 2009)
Through Silicon Via-Based Grid for Thermal Control in 3D Chips J.L. Ayala, A. Sridhar, V. Pangracious, D. Atienza, Y. Leblebici, NANO-NET 2009, (0, 2009)
Indicators show that the speed of transistor density and microprocessor performance improvements that drove the IT industry for the last 50 years are now limited by connectability issues between multiple cores and air-cooling rates. With its CMOS scaling engine slowing, the industry is striving to find new packaging altenatives to maintain the overall pace according to Moore’s law. While 2D scaling has been used in high performance processors for several decades, the third dimension has not yet been tackled. Recent progress in the fabrication of through silicon vias has opened new avenues for high density area array interconnects between stacked processor and memory chips. Such three-dimensional integrated circuits are attractive solutions for overcoming the present barriers encountered in interconnect scaling, thus offering an opportunity to continue the CMOS performance trends over the next few decades. 
