3D Stacked Architectures with Interlayer Cooling
Indicators show that the speed of transistor density and microprocessor performance improvements that drove the IT industry for the last 50 years are now limited by connectability issues between multiple cores and air-cooling rates. With its CMOS scaling engine slowing, the industry is striving to find new packaging altenatives to maintain the overall pace according to Moore’s law. While 2D scaling has been used in high performance processors for several decades, the third dimension has not yet been tackled. Recent progress in the fabrication of through silicon vias has opened new avenues for high density area array interconnects between stacked processor and memory chips. Such three-dimensional integrated circuits are attractive solutions for overcoming the present barriers encountered in interconnect scaling, thus offering an opportunity to continue the CMOS performance trends over the next few decades.  

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Our researchers in the media

Posters from 2013

Intra chip stack fluidic cooling: the CMOSAIC demonstrator
Yassir Madhour, Michail Zervas, Brian P. D%u2019Entremont, Thomas Brunschwiler, Gerd Schlottig, Bruno Michel, Yusuf Leblebici and John Richard Thome

Integrated Water Cooling of 3D Electronic Chips
Adrian Renfer, Fabio Alfieri, Manish K. Tiwari, Thomas Brunschwiler, Bruno Michel, Dimos Poulikakos

Superhydrophobic surfaces
Michael Rossier, Daniela Paunescu, Wendelin Jan Stark

EDA for CMOSAIC: a new generation of CAD tools for liquid-cooled 2D/3D ICs
Arvind Sridhar, Mohamed Sabry, Alessandro Vincenzi, David Atienza, Thomas Brunschwiler


Posters from 2012

Posters from 2011

Superhydrophobic surfaces
Michael Rossier, Jan Wendelin Stark

Integrated Single Phase Water Cooling of 3D Chips: Modeling and Experiments
Adrian Renfer, Fabio Alfieri, Manish Tiwari, Igor Zinovik, Thomas Brunschwiler, Bruno Michel, Dimos Poulikakos

Die-Level Through-Silicon-Via (TSV) Fabrication Platform
Yuksel Temiz, Michael Zervas, Carlotta Guiducci, Yusuf Leblebici

Wafer level TSV compatible to liquid cooling high performance CMOS
Michael Zervas, Yuksel Temiz, Yusuf Leblebici


Notable publications

Water Nanoconfinement Induced Thermal Enhancement at Hydrophilic Quartz Interfaces
M. Hu, J. V. Goicochea, B. Michel, D. Poulikakos,
Nano Letters (2010)

Validation of the Porous-Medium Approach to Model Interlayer-Cooled 3D-Chip Stacks
T. Brunschwiler, S. Paredes, U. Drechsler, B. Michel, W. Cesar, G. Töral, Y. Temiz, Y. Leblebici,
IEEE International Conference on 3D System Integration (3DIC 2009), (2009)

Two-phase flow boiling of R134a in a multi-microchannel heat sink for microprocessor cooling
Y. Madhour, J. Olivier, E.C. Patry, S. Paredes, B. Michel, J.R. Thome,
THERMINIC Conference (2010)

Two-phase flow boiling of R134a in a multi-microchannel heat sink for microprocessor cooling
Y. Madhour, J. Olivier, E.C. Patry, S. Paredes, B. Michel, and J.R. Thome,
THERMINIC Conference Proceedings (2011)

John Thome

Expert in microscale two-phase flow and heat transfer and modeling of micro-evaporators

    David Atienza


    Expert in thermal modeling of multiprocessor architectures and thermal management, hardware/software co-design methods
    Yusuf Leblebici


    Expert in chip design, intelligent detector, VLSI design, high-level specification and synthesis, sensors development
    Bruno Michel

    IBM Zürich [Industrial Partner]

    Expert in thermal packaging of high performance computers
    Dimos Poulikakos


    Expert in micro-scale liquid phase cooling, nanofluid heat transfer and heat transfer modeling
    Jan Wendelin Stark


    Expert in catalyst nanoparticles, nanomaterials and conception and characterization of nanofluids
Project Members' Network within Nano-Tera
Our researchers in the media


Notable publications