Indicators show that the speed of transistor density and microprocessor performance improvements that drove the IT industry for the last 50 years are now limited by connectability issues between multiple cores and air-cooling rates. With its CMOS scaling engine slowing, the industry is striving to find new packaging altenatives to maintain the overall pace according to Moore’s law. While 2D scaling has been used in high performance processors for several decades, the third dimension has not yet been tackled. Recent progress in the fabrication of through silicon vias has opened new avenues for high density area array interconnects between stacked processor and memory chips. Such three-dimensional integrated circuits are attractive solutions for overcoming the present barriers encountered in interconnect scaling, thus offering an opportunity to continue the CMOS performance trends over the next few decades.
Angle-Of-Attack Investigation of Pin Fin Arrays in Non-Uniform Heat-Removal Cavities for Interlayer Cooled Chip Stacks T. Brunschwiler, S. Paredes, U. Drechsler, B. Michel, B. Wunderle, H. Reichl, SEMI-Therm, San Jose, CA, (2011)
Attaining Single-Chip, High-Performance Computing Through 3D Systems with Active Cooling A. K. Coskun, D. Atienza, M. Sabry, J. Meng, IEEE Micro Magazine, ISSN: 0272-1732, IEEE Press, (7, 2011)
Cooling of next generation computer chips: parametric study for single- and two-phase cooling Y. Madhour, S. Zimmermann, J. Olivier, J.R. Thome, B. Michel and D. Poulikakos THERMINIC Conference Proceedings (7, 2011)
Design Methods and Tools for 3D Integration G. De Micheli, V. Pavlidis, D. Atienza Alonso, and Y. Leblebici, In Proceedings of the Symposium on VLSI Technology", (7, 2011)